Hewlett-Packard Develops Chips With Nanowires

Hewlett-Packard plans to publish a paper outlining how the performance of certain types of chips can be enhanced by replacing the communication wires inside the chips with an overhead grid of nanowires.

This innovative architectural concept hopes to address the problem of how to continue to shrink chips and the components inside chips.

To date it has been possible to both enhance performance and reduce production costs by reducing the size of transistors and interconnects (the metallic wires that link up transistors) every two years.

It has, however, become increasing difficult and more expensive to downsize these parts without compromising performance, energy efficiency or cost.

HP’s planned move to a crossbar structure would essentially change the shrinkage formula. By removing the traditional interconnects, the size of a given chip would naturally shrink substantially.

The move would enhance performance, but as chips could still be made out of traditional transistors cost might decline because there would be no need to invest in new semiconductor manufacturing equipment. Power consumption is also expected to fall.

HP has demonstrated how the crossbar structure can be used to improve memory chips, compensate for manufacturing defects and help circuits do calculations.

It has created a simulation of a field-programmable gate array (FPGA) with a crossbar grid, and it hopes to have a prototype by the end of the year.

HP’s research paper will be published in the January 24 edition of Nanotechnology.